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LTM9001-GA 16-Bit IF/Baseband Receiver Subsystem FeaTures
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DescripTion
The LTM(R)9001 is an integrated System in a Package (SiP) that includes a high-speed 16-bit A/D converter, matching network, anti-aliasing filter and a low noise, differential amplifier with fixed gain. It is designed for digitizing wide dynamic range signals with an intermediate frequency (IF) range up to 300MHz. The amplifier allows either AC- or DCcoupled input drive. A lowpass or bandpass filter network can be implemented with various bandwidths. Contact Linear Technology regarding semi-custom configurations, (see Table 1.) The LTM9001 is perfect for IF receivers in demanding communications applications, with AC performance that includes 78dBFS noise floor and 87dB spurious free dynamic range (SFDR) at 5MHz (LTM9001-GA). The digital outputs are single-ended CMOS. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.3V. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
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Integrated 16-Bit, High-Speed ADC, Passive Filter and Fixed Gain Differential Amplifier Up to 300MHz IF Range Lowpass and Bandpass Filter Versions Low Noise, Low Distortion Amplifiers Fixed Gain: 8dB, 14dB, 20dB or 26dB 50, 200 or 400 Input Impedance 78dB SNR, 87dB SFDR (LTM9001-GA) Integrated Bypass Capacitance, No External Components Required Optional Internal Dither Optional Data Output Randomizer 3.3V Single Supply Power Dissipation: 550mW (LTM9001-GA) Clock Duty Cycle Stabilizer 11.25mm x 11.25mm x 2.32mm LGA Package
applicaTions
n n n n n
Telecommunications High Sensitivity Receivers Imaging Systems Spectrum Analyzers ATE
Typical applicaTion
Simplified IF Receiver Channel
VCC SENSE VDD = 3.3V LTM9001-GA 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
64k Point FFT, fIN = 5MHz, -1dBFS, PGA = 0
LTM9001-GA 0VDD = 0.5V TO 3.6V AMPLITUDE (dBFS)
D15 IN- SAW LO IN+ DIFFERENTIAL FIXED GAIN AMPLIFIER GND CLK ADC CONTROL PINS ANTI-ALIAS FILTER 16-BIT 25Msps ADC D0 CLKOUT OF OGND
9001-GA TA01
* * *
RF
HD2
HD3
0.0
2.5
5.0 7.5 10.0 FREQUENCY (MHz)
12.5
9001-GA TA01a
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LTM9001-GA absoluTe MaxiMuM raTings
(Notes 1, 2)
pin conFiguraTion
ALL ELSE = GND TOP VIEW CONTROL 1 J IN- IN+ H G F VCC E DNC D C CLK B A CONTROL VDD OGND OVDD OGND OVDD 2 3 4 DATA 5 6 7 8 9 OGND
Supply Voltage (VCC) ................................ -0.3V to 3.6V Supply Voltage (VDD) ................................... -0.3V to 4V Digital Output Supply Voltage (OVDD) .......... -0.3V to 4V Analog Input Current (IN+, IN-) ............................10mA Digital Input Voltage (Except AMPSHDN) ................. -0.3V to (VDD + 0.3V) Digital Input Voltage (AMPSHDN)..............................-0.3V to (VCC + 0.3V) Digital Output Voltage ................-0.3V to (OVDD + 0.3V) Operating Temperature Range LTM9001C................................................ 0C to 70C LTM9001I.............................................-40C to 85C Storage Temperature Range...................-45C to 125C Maximum Junction Temperature........................... 125C
LGA PACKAGE TJMAX = 125C, JA = 15C/W, JC = 19C/W JA DERIVED FROM 60mm 70mm PCB WITH 4 LAYERS WEIGHT = 0.71g
orDer inForMaTion
LEAD FREE FINISH LTM9001CV-GA#PBF LTM9001IV-GA#PBF TRAY LTM9001CV-GA#PBF LTM9001IV-GA#PBF PART MARKING* PACKAGE DESCRIPTION LTM9001V-GA LTM9001V-GA 81-Lead (11.25mm x 11.25mm x 2.3mm) LGA 81-Lead (11.25mm x 11.25mm x 2.3mm) LGA TEMPERATURE RANGE 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
SYMBOL GDIFF GTEMP VINCM VIN RINDIFF CINDIFF VOS PARAMETER Gain Gain Temperature Drift Input Common Mode Voltage Range Input Voltage Range at -1dBFS Differential Input Impedance Differential Input Capacitance Offset Error (Note 6) Offset Drift Full-Scale Drift CONDITIONS DC, LTM9001-GA fIN = 5MHz VIN = Maximum, (Note 3) (IN+ + IN-)/2 LTM9001-GA at 5MHz LTM9001-GA Includes Parasitic Including Amplifier and ADC (LTM9001-GA) Including Amplifier and ADC Internal Reference External Reference
l l
elecTrical characTerisTics
MIN 7.2
TYP 8 8 2 1.0-1.6 900 400 1
MAX 8.8
UNITS dB mdB/C V mVP-P pF mV V/C ppm/C ppm/C
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-50
-10 10 30 15
LTM9001-GA
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
SYMBOL CMRR ISENSE IMODE IOE tAP tJITTER PARAMETER Common Mode Rejection Ratio SENSE Input Leakage Current MODE Pin Pull-Down Current to GND OE Pin Pull-Down Current to GND Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter 0V < SENSE < VDD (Note 9)
l
elecTrical characTerisTics
CONDITIONS
MIN -3
TYP 60
MAX 3
UNITS dB A A A ns fsRMS
10 10 1 70
converTer characTerisTics
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Transition Noise
The l indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
CONDITIONS
l
MIN 16
l l
TYP 2.4 0.3 1
MAX 8 1
UNITS Bits LSB LSB LSBRMS
Differential Input LTM9001-GA (Note 5) Differential Input External Reference
DynaMic accuracy
SYMBOL SNR SFDR SFDR S/(N+D) SFDR SFDR IMD3 IIP3 PARAMETER Signal-to-Noise Ratio
The l indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 4)
CONDITIONS 5MHz Input (PGA = 0) 5MHz Input (PGA = 1) 5MHz Input (PGA = 0) 5MHz Input (PGA = 1) 5MHz Input (PGA = 0) 5MHz Input (PGA = 1) 5MHz Input (PGA = 0) 5MHz Input (PGA = 1) 5MHz Input (PGA = 0) 5MHz Input (PGA = 1) 5MHz Input (PGA = 0) 5MHz Input (PGA = 1) fIN = 5MHz fIN = 5MHz
l l l l l l
MIN 76 76 91 75 91 93
TYP 78 75.4 87 89.8 100 99 77.4 74.8 105 107.5 107 109 85 36.5
MAX
UNITS dBFS dBFS dBc dBc dBc dBc dBFS dBFS dBFS dBFS dBFS dBFS dB dBm
Spurious Free Dynamic Range, 2nd or 3rd Harmonic Spurious Free Dynamic Range 4th or Higher Signal-to-Noise Plus Distortion Ratio Spurious Free Dynamic Range at -15dBFS, Dither "OFF" Spurious Free Dynamic Range at -15dBFS, Dither "ON" Third Order Intermodulation Distortion; 1MHz Tone Spacing, 2 Tones at -7dBFS Equivalent Third Order Input Intercept Point, 2 Tone
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LTM9001-GA
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
SYMBOL VIH VIL IIN CIN VIH VIL IIH IIL CIN Logic Outputs OVDD = 3.3V VOH VOL ISOURCE ISINK OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL High Level Output Voltage Low Level Output Voltage VDD = 3.3V, IO = -200A VDD = 3.3V, IO = 1.6A 1.79 0.1 V V High Level Output Voltage Low Level Output Voltage VDD = 3.3V, IO = -200A VDD = 3.3V, IO = 1.6mA 2.49 0.1 V V High Level Output Voltage Low Level Output Voltage Output Source Current Output Sink Current VDD = 3.3V, IO = -10A VDD = 3.3V, IO = -200A VDD = 3.3V, IO = 10A VDD = 3.3V, IO = 1.6mA VOUT = 0V VOUT = 3.3V
l l
DigiTal inpuTs anD ouTpuTs
PARAMETER High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance High Level Input Voltage Low Level Input Voltage Input High Current Input Low Current Input Capacitance
CONDITIONS VDD = 3.3V VDD = 3.3V VIN = 0V to VDD (Note 7) VCC = 3.3V VCC = 3.3V VIN = 2V VIN = 0.8V (Note 7)
l l l l l
MIN 2
TYP
MAX
UNITS V
Logic Inputs (DITH, PGA, ADCSHDN, RAND, CLK, OE) 0.8 10 1.5 2 0.8 1.3 0.1 1.5 V A pF V V A A pF
Logic Inputs (AMPSHDN)
3.1
3.299 3.29 0.01 0.1 -50 50 0.4
V V V V mA mA
power requireMenTs
SYMBOL VDD VCC ICC PSHDN OVDD IVDD PDISS PDISS(TOTAL) PARAMETER ADC Analog Supply Voltage Amplifier Supply Voltage Amplifier Supply Current Total Shutdown Power Output Supply Voltage Analog Supply Current ADC Power Dissipation Total Power Dissipation
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS (Note 8)
l l l
MIN 3.135 2.85
TYP 3.3 100 10
MAX 3.465 3.5 136 3.6
UNITS V V mA mW V mA mW mW
AMPSHDN = ADCSHDN = 3.3V (Note 8) LTM9001-GA LTM9001-GA LTM9001-GA
l l l
0.5 66 220 550
80 265
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LTM9001-GA TiMing characTerisTics
SYMBOL fS tL tH CMOS Output Mode tD tC tSKEW CLK to DATA Delay CLK to CLKOUT Delay DATA to CLKOUT Skew Data Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: Gain is measured from IN+/IN- through the ADC. Note 4: VCC = VDD = 3.3V, fSAMPLE = maximum sample frequency, input range = -1dBFS with PGA = 0 with differential drive, AC-coupled inputs, unless otherwise noted. (Note 7) (Note 7) (tC - tD) (Note 7)
l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
PARAMETER Sampling Frequency (Note 8) CLK Low Time (Note 7) CLK High Time (Note 7) CONDITIONS LTM9001-GA Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On
l l l l l
MIN 1 18.9 5 18.9 5 1.3 1.3 -0.6
TYP 20 20 20 20 3.1 3.1 0 7
MAX 25 500 500 500 500 4.9 4.9 0.6
UNITS MHz ns ns ns ns ns ns ns Cycles
Note 5: Integral nonlinearity is defined as the deviation of a code from a "best fit straight line" to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the voltage applied between the IN+ and IN- pins required to make the output code flicker between 0000 0000 0000 0000 and 1111 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. Note 9: Leakage current will experience transient at power up. Keep resistance <1k.
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LTM9001-GA TiMing DiagraM
tAP ANALOG INPUT N+1 N+2 tL CLK tD D0-D15, OF CLKOUT + CLKOUT - tC N-7 N-6 N-5 N-4 N-3 tH N+3 N+4
N
9001GA TD03
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LTM9001-GA Typical perForMance characTerisTics
IF Frequency Response
0 -1 IMPEDANCE MAGNITUDE ( ) -2 FILTER GAIN (dB) -3 -4 -5 -6 -7 -8 -9 -10 0 1 10 FREQUENCY (MHz) 100
9001-GA G01
Input Impedance vs Frequency
400 350 300 250 200 150 100 50 0 1 MAGNITUDE PHASE 10 100 FREQUENCY (MHz) 40 32 24 16 8 0 -8 -16 -24 -32 1000
9001-GA G02
SNR vs Frequency
80 79 78 IMPEDANCE PHASE (C) 77 SNR (dB) 76 75 74 73 72 71 70 0 1 10 FREQUENCY (MHz) 100
9001-GA G03
Integral Non-Linearity (INL) vs Output Code
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 - 0.5 - 1.0 - 1.5 - 2.0 - 2.5 - 3.0 - 3.5 - 4.0 1.0 0.8 0.6
Differential Non-Linearity (DNL) vs Output Code
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
64k Point FFT, fIN = 5MHz, -15dBFS, PGA = 0, RAND "0n", Dither "On"
0.2 0.0 -0.2 -0.4 -0.6 -0.8
0
16384
32768 49152 OUTPUT CODE
65536
9001-GA G04
- 1.0
AMPLITUDE (dBFS)
DNL ERROR (LSB)
INL ERROR (LSB)
0.4
0
16384
32768 49152 OUTPUT CODE
65536
9001-GA G05
0.0
2.5
5.0 7.5 10.0 FREQUENCY (MHz)
12.5
9001-GA G06
64k Point FFT, fIN = 5MHz, -1dBFS, PGA = 0, RAND "Off", Dither "Off"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
64k Point FFT, fIN = 5MHz, -1dBFS, PGA = 1, RAND "Off", Dither "Off"
0 -10 -20 -30 -40 -50 -60 -70 -80 -90
64k Point 2-Tone FFT, fIN = 4.9MHz, and fIN = 5.1MHz, -7dBFS Per Tone, PGA = 0, RAND "Off", Dither "Off"
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
HD2
HD3
HD2
HD3
AMPLITUDE (dBFS) 12.5
0.0
2.5
5.0 7.5 10.0 FREQUENCY (MHz)
12.5
0.0
2.5
5.0 7.5 10.0 FREQUENCY (MHz)
-100 -110 -120 -130 0.0
2.5
9001-GA G07
9001-GA G08
5.0 7.5 FREQUENCY (MHz)
10
12.5
9001-GA G09
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LTM9001-GA pin FuncTions
Supply Pins VCC (Pins E1, E2): 3.3V Analog Supply Pin for Amplifier. The voltage on this pin provides power for the amplifier stage only and is internally bypassed to GND. VDD (Pins E5, D5): 3.3V Analog Supply Pin for ADC. This supply is internally bypassed to GND. OVDD (Pins A6, G9): Positive Supply for the ADC Output Drivers. This supply is internally bypassed to OGND. GND (Pins A1, A2, A4, B2, B4, C2, C4, D1, D2, D4, E4, F1, F2, F4, G2, G4, H2, H4, J1, J2, J4): Analog Ground. OGND (Pins A5, A9, G8, J9): ADC Output Driver Ground. Analog Inputs IN+ (Pin G1): Positive (Noninverting) Amplifier Input. IN- (Pin H1): Negative (Inverting) Amplifier Input. DNC (Pins C3, D3): Do Not Connect. These pins are used for testing and should not be connected on the PCB. They may be soldered to unconnected pads and should be well isolated. The DNC pins connect to the signal path prior to the ADC inputs; therefore, care should be taken to keep other signals away from these sensitive nodes. NC (See Pin Configuration Table for Pin Locations): No Connect. CLK (Pin B1): Clock Input. The sampled analog input is held on the falling edge of CLK. The output data may be latched on the rising edge of CLK. Control Inputs SENSE (Pin J3): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set the maximum full-scale input range. AMPSHDN (Pin H3): Power Shutdown Pin for Amplifier. This pin is a logic input referenced to analog ground. AMPSHDN = low results in normal operation. AMPSHDN = high results in powered down amplifier with typically 3mA amplifier supply current. MODE (Pin G3): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2's complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2's complement output format and disables the clock duty cycle stabilizer. RAND (Pin F3): Digital Output Randomization Selection Pin. RAND = low results in normal operation. RAND = high selects D1 to D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. This mode of operation reduces the effects of digital output interference. PGA (Pin E3): Programmable Gain Amplifier Control Pin. PGA = low selects the normal (maximum) input voltage range. PGA = high selects a 3.5dB reduced input range for slightly better distortion performance at the expense of SNR. ADCSHDN (Pin B3): Power Shutdown Pin for ADC. ADCSHDN = low results in normal operation. ADCSHDN = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. DITH (Pin A3): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of this data sheet for details on dither operation. OE (Pin F5): Output Enable Pin. Low enables the digital output drivers. High puts digital outputs in Hi-Z state. Digital Outputs D0 to D15 (See Pin Configuration Table for Pin Locations): Digital Outputs. D15 is the MSB and D0 the LSB. CLKOUT+ (Pin E7): Inverted Data Valid Output. CLKOUT+ will toggle at the sample rate. Latch the data on the rising edge of CLKOUT+. CLKOUT - (Pin E6): Data Valid Output. CLKOUT - will toggle at the sample rate. Latch the data on the falling edge of CLKOUT -. OF (Pin G5): Over/Under Flow Digital Output. OF is high when an over or under flow has occurred.
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LTM9001-GA pin FuncTions
Pin Configuration
1 J H G F E D C B A GND IN- IN+ GND VCC GND NC CLK GND 2 GND GND GND GND VCC GND GND GND GND 3 SENSE AMPSHDN MODE RAND PGA DNC DNC ADCSHDN DITH 4 GND GND GND GND GND GND GND GND GND 5 D14 NC OF OE VDD VDD D0 NC OGND 6 NC NC D15 NC CLKOUT- NC NC NC OVDD 7 D12 NC D13 D9 CLKOUT D6 D4 D1 NC 8 NC NC OGND NC NC NC NC D3 D2 9 OGND D11 OVDD D10 D8 D7 D5 NC OGND
Top View of LGA Pinout (Looking Through Component)
ALL ELSE = GND TOP VIEW CONTROL 1 J IN- IN+ H G F VCC E DNC D C CLK B A CONTROL VDD OGND OVDD
9001-GA LGA01
DATA 4 5 6 7 8 9 OGND
2
3
OVDD
OGND
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LTM9001-GA
FuncTional block DiagraM
0
VCC VDD VDD ANTI-ALIAS FILTER INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE DITHER SIGNAL GENERATOR SHIFT REGISTER AND ERROR CORRECTION INTERNAL CLOCK SIGNALS ADC REFERENCE OVDD VOLTAGE REFERENCE PGA LOW JITTER CLOCK DRIVER RANGE SELECT D0...D15 CONTROL LOGIC OUTPUT DRIVERS CLKOUT + CLKOUT - OF
9001-GA BD
VCC
IN+
IN-
INPUT AMPLIFIER
AMPSHDN
SENSE
PGA GND
CLK
ADCSHDN
RAND MODE
OE
DITH
OGND
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LTM9001-GA operaTion
DYNAMIC PERFORMANCE DEFINITIONS Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. Signal-to-Noise Ratio The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the first five harmonics. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = -20Log (V22 + V32 + V42 + ...Vn2 )/V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. Intermodulation Distortion If the input signal consists of more than one spectral component, the transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the input, nonlinearities in the transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, the 3rd order IMD terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is defined as the ration of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full scale and expressed in dBFS. Aperture Delay Time Aperture Delay is the time from when a rising ENC+ equals the ENC- voltage to the instant that the input signal is held by the sample and-hold circuit. Or, for single-ended CLK versions, the time from when CLK reaches 0.45 of VDD to the instant that the input signal is held by the sampleand-hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = -20log (2 * fIN * tJITTER) DESCRIPTION The LTM9001 is an integrated System in a Package (SiP) Module (R) receiver that includes a high-speed, sampling 16-bit A/D converter, matching network, anti-aliasing filter and a low noise, differential amplifier with fixed gain. It
Module is a registered trademark of Linear Technology Corporation.
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LTM9001-GA operaTion
is designed for digitizing high frequency, wide dynamic range signals with an intermediate frequency (IF) range up to 300MHz. The following sections describe in further detail the functional operation of the LTM9001. The SiP technology allows
AMPLIFIER ADC INPUT NETWORK ADC
for the application. The final result is a fully integrated, accurately tested and reliable solution. For more details on the semi-custom receiver subsystem program, contact Linear Technology. Note that not all combinations of options in Table 1 are possible at this time and specified performance may differ significantly from existing values. The higher speed options support LVDS or CMOS outputs and are available on a separate data sheet. This data sheet discusses CMOS only versions which have a different pin assignment. AMPLIFIER INFORMATION The amplifiers used in the LTM9001 are low noise and low distortion fully differential ADC drivers. The amplifiers are very flexible in terms of I/O coupling. They can be AC- or DC-coupled at the inputs. Users are advised to keep the input common mode voltage between 1V and 1.6V for proper operation. If the inputs are AC-coupled, the input common mode voltage is automatically biased. The input signal can be either single-ended or differential with almost no difference in distortion performance. ADC INPUT NETWORK The passive network between the amplifier output stage and the ADC input stage can be configured for bandpass or lowpass response with different cutoff frequencies and bandwidths. The LTM9001-GA, for example, implements a 1-pole lowpass filter with 10MHz bandwidth. Note that the filter attenuates the signal at 10MHz by 0.2dB, making the overall gain of the subsystem 7.8dB. For production test purposes the filter is designed to allow DC inputs into the ADC. CONVERTER INFORMATION The analog-to-digital converter (ADC) is a CMOS pipelined multistep converter with a front-end PGA. As shown in the Functional Block Diagram, the converter has five pipelined ADC stages; a sampled analog input will result in a digitized
9001-GA F01
Figure 1. Basic Functional Elements
the LTM9001 to be customized and this is described in the first section. The remaining outline follows the basic functional elements as shown in Figure 1. SEMI-CUSTOM OPTIONS The Module construction affords a new level of flexibility in application-specific standard products. Standard ADC and amplifier components can be integrated regardless of their process technology and matched with passive components to a particular application. The LTM9001-AA, on a separate data sheet, is configured with a 16-bit ADC sampling at rates up to 130Msps. The amplifier gain is 20dB with an input impedance of 200 and an input range of 233mVP-P. The matching network is designed to optimize the interface between the amplifier output and the ADC under these conditions. Additionally, there is a 2-pole bandpass filter designed for 162.5MHz 25MHz. However, other options are possible through Linear Technology's semi-custom development program. Linear Technology has in place a program to deliver other speed, resolution, IF range, gain and filter configurations for a wide range of applications. See Table 1 for the LTM9001 configuration and potential options. These semi-custom designs are based on existing ADCs and amplifiers with an appropriately modified matching network. The final subsystem is then tested to the exact parameters defined
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LTM9001-GA operaTion
Table 1. Semi-Custom Options
AMPLIFIER IF AMPLIFIER INPUT AMPLIFIER FILTER ADC SAMPLE RATE RANGE IMPEDANCE GAIN 300MHz 200 20dB 162.5MHz BPF, 50MHz BW 130Msps 300MHz 200 14dB 70MHz BPF, 25MHz BW 130Msps 300MHz 400 8dB DC-300MHz LPF 160Msps 300MHz 400 8dB DC-10MHz LPF 25Msps Select Combination of Options from Columns Below DC-300MHz 50 26dB LPF TBD 160Msps DC-140MHz 200 20dB BPF TBD 130Msps DC-70MHz 200 14dB 105Msps DC-35MHz 400 8dB 80Msps 200 6dB 65Msps 40Msps 25Msps 10Msps ADC RESOLUTION 16-bit 16-bit 16-bit 16-bit 16-bit 14-bit OUTPUT LVDS/CMOS LVDS/CMOS LVDS/CMOS CMOS LVDS/CMOS LVDS/CMOS CMOS CMOS CMOS CMOS CMOS CMOS PART NUMBER LTM9001-AA LTM9001-AD LTM9001-BA LTM9001-GA
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LTM9001-GA applicaTions inForMaTion
INPUT SPAN The LTM9001 is configured with a fixed input span and input impedance. With the amplifier gain and the ADC input network described above for LTM9001-GA, the fullscale input range of the driver circuit is 1000mVP-P. The recommended ADC input span is achieved by tying the SENSE pin to VDD. However, the ADC input span can be changed by applying a DC voltage to the SENSE pin. Input Impedance and Matching The differential input impedance of the LTM9001 can be 50, 200 or 400. In some applications the differential inputs may need to be terminated to a lower value impedance, e.g. 50, in order to provide an impedance match for the source. Several choices are available. One approach is to use a differential shunt resistor (Figure 2). Another approach is to employ a wideband transformer (Figure 3). Both methods provide a wideband match. The termination resistor or the transformer must be placed close to the input pins in order to minimize the reflection due to input mismatch.
Table 2. Differential Amplifier Input Termination Values
ZIN 400 200 50 RT Figure 2 57 66.5 None
25 IN+ ZIN/2 LTM9001-GA RF
+ -
VIN RT
25
IN-
ZIN/2
RF
9001-GA F02
Figure 2. Input Termination for Differential 50 Input Impedance Using Shunt Resistor (See Table 2 for RT Values)
25
IN+
ZIN/2
LTM9001-GA RF
+ -
VIN
**
25
IN-
ZIN/2
RF
9001-GA F03
Figure 3. Input Termination for Differential 50 Input Impedance Using a Wideband Transformer
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LTM9001-GA applicaTions inForMaTion
Alternatively, one could apply a narrowband impedance match at the inputs for frequency selection and/or noise reduction. Referring to Figure 4, amplifier inputs can be easily configured for single-ended input without a balun. The signal is fed to one of the inputs through a matching network while the other input is connected to the same impedance. In general, the single-ended input impedance and termination resistor RT are determined by the combination of RS, ZIN/2 and RF .
Table 3. Single-Ended Amplifier Input Termination Values
ZIN 400 200 50 RT Figure 4 59 68.5 150
VIN RT Rs/2 IN+ ZIN/2
RS 50 0.1F IN+ ZIN/2 LTM9001-GA RF
+ -
VIN RT 0.1F
RS/RT
0.1F
IN-
ZIN/2
RF
9001-GA F04
Figure 4. Input Termination for Differential 50 Input Impedance Using Shunt Resistor
LTM9001-GA RF
The LTM9001 amplifier is stable with all source impedances. The overall differential gain is affected by the source impedance in Figure 5: AV = | VOUT/VIN | = (1000/(RS + ZIN/2)) The noise performance of the amplifier also depends upon the source impedance and termination. For example, an input 1:4 transformer in Figure 3 improves the input noise figure by adding 6dB voltage gain at the inputs. Reference and SENSE Pin Operation Figure 6 shows the converter reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifier and control circuit. There are three modes of reference operation: Internal Reference, 1.25V external reference or 2.5V external reference. To use the internal reference, tie the SENSE pin to VDD. To use an external reference, simply apply either a 1.25V or 2.5V reference voltage to the SENSE input pin. Both 1.25V and 2.5V applied to SENSE will result in the maximum full-scale range.
+ -
Rs/2
IN-
ZIN/2
RF
9001-GA F05
Figure 5. Calculate Differential Gain
TIE TO VDD TO USE INTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 1.25V REFERENCE
RANGE SELECT AND GAIN CONTROL SENSE PGA
INTERNAL ADC REFERENCE
2.5V BANDGAP REFERENCE
9001-GA F06
Figure 6. Reference Circuit
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LTM9001-GA applicaTions inForMaTion
PGA Pin The PGA pin selects between two gain settings for the ADC front-end. PGA = low selects the maximum input span; PGA = high selects a 3.5dB lower input span. The high input range has the best SNR. For applications with high linearity requirements, the low input range will have improved distortion; however, the SNR will be 1.8dB worse. See the Typical Performance Characteristics section. Driving the Clock or Encode Inputs Certain versions of LTM9001 have differential encode inputs, others have a single-ended clock input.The noise performance of the converter can depend on the encode signal quality as much as the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies), take the following into consideration: 1. Differential drive should be used. 2. Use the largest amplitude possible. If using transformer coupling, use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a fixed frequency sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to VDD. Each input may be driven from ground to VDD for single-ended drive. The encode clock inputs have a differential 100 input impedance. For 50 inputs e.g. signal generators, an additional 100 impedance will provide an impedance match, as shown in Figure 7b.
SINUSOIDAL CLOCK INPUT ENC+ 100 ENC- VDD 1.6V 6k
The single-ended CLK input on LTM9001-GA can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can be used along with a low-jitter squaring circuit before the CLK pin (Figure 8).
LTM9001-TBD VDD TO INTERNAL ADC CLOCK DRIVERS
VDD
1.6V 6k
9001-GA F07a
Figure 7a. Equivalent Encode Input Circuit
0.1F T1 50 8.2pF 0.1F 50 0.1F
LTM9001-TBD ENC+
100
T1 = M/A-COM ETC1-1-13
Figure 7b. Transformer Driven Encode
CLEAN 3.3V SUPPLY FERRITE BEAD 0.1F 0.1F 1k
Figure 8. Sinusoidal Single-Ended CLK Drive
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*
56
*
4.7F CLK 1k NC7SVU04
ENC-
9001-GA F07b
LTM9001-GA
9001-GA F09a
LTM9001-GA applicaTions inForMaTion
Maximum and Minimum Encode Rates The maximum encode rate for the LTM9001-GA is 25Msps. For the ADC to operate properly the CLK signal should have a 50% (5%) duty cycle. Each half cycle must have at least 18.9ns (LTM9001-GA) for the ADC internal circuitry to have enough settling time for proper operation. An optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. This circuit uses the rising edge of CLK or ENC to sample the analog input. The falling edge of CLK or ENC is ignored and an internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin must be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the sample rate is determined by the droop of the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTM9001 is 1Msps. DIGITAL OUTPUTS Digital Output Buffers Figure 9 shows an equivalent circuit for a single output buffer in CMOS mode. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50 to external circuitry and eliminates the need for external damping resistors.
LTM9001-GA VDD VDD
OVDD
0.5V TO 3.6V
OVDD DATA FROM LATCH PREDRIVER LOGIC 43 TYPICAL DATA OUTPUT OGND
9001-GA F10
Figure 9. Equivalent Circuit for a Digital Output Buffer
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LTM9001-GA applicaTions inForMaTion
As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTM9001 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the output may be used but is not required since the ADC has a series resistor of 43 on chip. Lower OVDD voltages will also help reduce interference from the digital outputs. Data Format The LTM9001 parallel digital output can be selected for offset binary or 2's complement format. The format is selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3VDD , 2/3VDD and VDD. An external resistive divider can be used to set the 1/3VDD and 2/3VDD logic levels. Table 5 shows the logic states for the MODE pin.
Table 5. MODE Pin Function
MODE 0V(GND) 1/3VDD 2/3VDD VDD OUTPUT FORMAT Offset Binary Offset Binary 2's Complement 2's Complement CLOCK DUTY CYCLE STABILIZER Off On On Off
D15 D0 D15 D14 D0 D14 LTM9001-GA D2 D0 OF RAND = HIGH, RANDOMIZER ENABLED RAND LTM9001-GA CLKOUT CLKOUT
OF
OF
D15
D15/D0
D14
D14/D0
D2
* * *
D2/D0
D1
D1/D0
D0
9001-GA F12
D0
Figure 10. Functional Equivalent of Digital Output Randomizer
PC BOARD FPGA CLKOUT
Overflow Bit An overflow output bit (OF) indicates when the converter is over-ranged or under-ranged. A logic high on the OF pin indicates an overflow or underflow.
* * *
D2
D1
D0 D1
D0
D0
9001-GA F13
Figure 11. Derandomizing a Randomized Digital Output
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Output Clock The ADC has a delayed version of the encode input available as a digital output. Both a non-inverted version, CLKOUT+, and an inverted version, CLKOUT-, are provided. The CLKOUT pins can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. Data will be updated as CLKOUT+ falls and CLKOUT- rises. Data may be latched on the rising edge of CLKOUT+ or the falling edge of CLKOUT-. Digital Output Randomizer Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude. The digital output is randomized by applying an exclusive-OR logic operation between the LSB and all other data output bits (see figure 10). To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the LSB and all other bits (see figure 11). The LSB, OF and CLKOUT output are not affected. The output randomizer function is active when the RAND pin is high. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. OVDD can be powered with any logic voltage up to the 3.6V. OGND can be powered with any voltage from ground up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. Internal Dither The LTM9001 is a 16-bit receiver subsystem with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels.
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LTM9001-GA applicaTions inForMaTion
As shown in Figure 12, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC will cause a small elevation in the noise floor of the ADC, as compared to the noise floor with dither off. For best noise performance with the dither signal on, the driving impedance connected across pins IN+/IN- should closely match that of the module (see Table 1). A source impedance that is resistive and matches that of the module within 10% will give the best results. Supply Sequencing The VCC pin provides the supply to the amplifier and the VDD pin provides the supply to the ADC. The amplifier and the ADC are separate integrated circuits within the LTM9001; however, there are no supply sequencing considerations beyond standard practice. It is recommended that the amplifier and ADC both use the same low noise, 3.3V supply, but the amplifier may be operated from a lower
LTM9001-GA CLKOUT OF D15 * * * D0
voltage level if desired. Both devices can operate from the same 3.3V linear regulator but place a ferrite bead between the VCC and VDD pins. Separate linear regulators can be used without additional supply sequencing circuitry if they have common input supplies. Grounding and Bypassing The LTM9001 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTM9001 has been optimized for a flow-through layout so that the interaction between inputs and digital outputs is minimized. A continuous row of ground pads facilitate a layout that ensures that digital and analog signal lines are separated as much as possible. The LTM9001 is internally bypassed with the amplifier (VCC) and ADC (VDD) supplies returning to a common ground (GND). The digital output supply (0VDD) is returned to OGND. Additional bypass capacitance is optional and may be required if power supply noise is significant. The differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup.
IN + IN - S/H AMP
16-BIT PIPELINED ADC CORE
DIGITAL SUMMATION
OUTPUT DRIVERS
CLOCK/DUTY CYCLE CONTROL
PRECISION DAC
MULTIBIT DEEP PSEUDO-RANDOM NUMBER GENERATOR
9001-GA F14
CLK
DITH DITHER ENABLE HIGH = DITHER ON LOW = DITHER OFF
Figure 12. Functional Equivalent Block Diagram of Internal Dither Circuit
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LTM9001-GA applicaTions inForMaTion
Heat Transfer Most of the heat generated by the LTM9001 is transferred through the bottom-side ground pads. For good electrical and thermal performance, it is critical that all ground pins are connected to a ground plane of sufficient area with as many vias as possible. Recommended Layout The high integration of the LTM9001 makes the PC board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary, see Figures 13 to 16. * Use large PCB copper areas for ground. This helps to dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. Common ground (GND) and output ground (OGND) are electrically isolated on the LTM9001, but can be connected on the PCB underneath the part to provide a common return path. * Use multiple ground vias. Using as many vias as possible helps to improve the thermal performance of the board and creates necessary barriers separating analog and digital traces on the board at high frequencies. * Separate analog and digital traces as much as possible, using vias to create high frequency barriers. This will reduce digital feedback that can reduce the signal-to-noise ratio (SNR) and dynamic range of the LTM9001. The quality of the paste print is an important factor in producing high yield assemblies. It is recommended to use a type 3 or 4 printing no-clean solder paste. The solder stencil design should follow the guidelines outlined in Application Note 100. The Module LGA Packaging Care and Assembly Instructions is available at http://www.linear. com/designtools/packaging/uModule_Instructions. The LTM9001 employs gold-finished pads for use with Pb-based or tin-based solder paste. It is inherently Pbfree and complies with the JEDEC (e4) standard. The materials declaration is available online at http://www. linear.com/designtools/leadfree/mat_dec.jsp.
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LTM9001-GA applicaTions inForMaTion
Figure 13. Layer 1
Figure 14. Layer 2
Figure 15. Layer 3
Figure 16. Layer 4
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aaa Z
11.250 BSC
X Y
2.17 - 2.47 J H 0.605 - 0.665 MOLD CAP SUBSTRATE 0.27 - 0.37
Z
0.25 45 CHAMFER 3
10.160 BSC 0.605 - 0.665
G F E D C B A 9 8 7 6 5 4 PACKAGE BOTTOM VIEW 3 2 1 PAD 1
package DescripTion
11.250 BSC 1.90 - 2.10
bbb Z
10.160 BSC
DETAIL A
PAD 1 CORNER 1.27 BSC
aaa Z
4
PACKAGE TOP VIEW
DETAIL A PACKAGE SIDE VIEW
3
PADS SEE NOTES
5.080
3.810
2.540
1.5875 1.270 0.9525
0.000
1.270
2.540
3.810
5.080
5.080
(Reference LTC DWG # 05-08-1809 Rev A)
3.810
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 4 LAND DESIGNATION PER JESD MO-222, SPP-010 AND SPP-020
LGA Package 81-Lead (11.25mm x 11.25mm x 2.32mm)
2.540
1.270
1.5875
0.9525
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR A MARKED FEATURE
COMPONENT PIN "A1" TRAY PIN 1 BEVEL
LTMXXXXXX Module
0.000
5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 81
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SYMBOL TOLERANCE aaa 0.15 bbb 0.10
PACKAGE IN TRAY LOADING ORIENTATION
LGA 81 1107 REV A
1.270
2.540
3.810
5.080
SUGGESTED PCB LAYOUT TOP VIEW
LTM9001-GA
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LTM9001-GA Typical applicaTion
LTM9001 with Ground-Referenced Single-Ended Input
3.3V RS 50 75 75 IN+ IN- 51.1 LTM9001-GA VCC
GROUND- REFERENCED SOURCE 0V
+ -
9001-GA TA02
relaTeD parTs
PART NUMBER LTC2202 LTC2203 LTC2204 LTC2205 LTC2206 LTC2207 LTC2208 LTC2209 LTC6400-8/LTC6400-14/ LTC6400-20/LTC6400-26 LTC6401-8/LTC6401-14/ LTC6401-20/LTC6401-26 DESCRIPTION 16-Bit, 10Msps ADC 16-Bit, 25Msps ADC 16-Bit, 40Msps ADC 16-Bit, 65Msps ADC 16-Bit, 80Msps ADC 16-Bit, 105Msps ADC 16-Bit, 130Msps ADC 16-Bit, 160Msps ADC Low Noise, Low Distortion Differential Amplifier for 300MHz IF, Fixed Gain of 8dB, 14dB, 20dB or 26dB Low Noise, Low Distortion Differential Amplifier for 140MHz IF, Fixed Gain of 8dB, 14dB, 20dB or 26dB COMMENTS 140mW, 81.6dB SNR, 100dB SFDR 220mW, 81.6dB SNR, 100dB SFDR 480mW, 79.1dB SNR, 100dB SFDR 610mW, 79dB SNR, 100dB SFDR 725mW, 77.9dB SNR, 100dB SFDR 900mW, 77.9dB SNR, 100dB SFDR 1250mW, 77.7dB SNR, 100dB SFDR 1450mW, 77.1dB SNR, 100dB SFDR 3V, 90mA, 39.5dBm OIP3 at 300MHz, 6dB NF 3V, 45mA, 45.5dBm OIP3 at 140MHz, 6dB NF
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
LT 0809 * PRINTED IN USA
FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2008

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